1. Field of the Invention
The present invention relates to jitter evaluation apparatus for receiving a digital test signal from which a clock signal is recovered, of the type comprising: a clock recovery circuit for recovering a recovered clock signal from said test signal; a synchronisation circuit for generating a synchronised system clock signal from said recovered clock signal; a sinusoid generator for generating a sinusoid signal from said synchronised system clock signal and a sampling analog to digital converter for sampling said sinusoid signal by said recovered clock signal to provide sinusoid samples.
The present invention also relates to a method for evaluating jitter.
2. Description of the Related Art
Systems for jitter evaluation are known in which a digital test signal is received, possibly from a device under test, from which a clock signal is recovered. An accurate system clock signal is generated from the recovered clock signal and a generator generates a sine wave synchronised to the accurate system clock signal. An analog to digital converter converts a sinusoid signal by sampling said signal based on the recovered clock signal. Thus, the sinusoid is generated by the accurate clock and then sampled by the recovered clock such that the recovered samples convey the inherent jitter.
When conveying high definition digital video signals it is known for these signals to include timing jitter in a low frequency range above 10 hz along with alignment jitter at frequencies above 100 khz. For a new device under test to be considered acceptable, both of these jitter components must have peak-to-peak values that lie below specified limits.
A known problem with test equipment of the aforesaid type is that sophisticated devices are often required in order to evaluate jitter components at the high frequencies used for high definition digital video transmission. Furthermore, further complications arise in terms of inherent accuracy and requirements for calibration.